1. Field of the Invention
This invention relates to integrated circuits and, more particularly, to circuitry for protecting integrated circuit components from damage caused by high slew rate, overvoltage and/or overcurrent conditions, such as those caused by electrostatic discharge.
2. Description of the Related Art
The following descriptions and examples are given as background only.
Integrated circuits are susceptible to damage from application of excessive electrical charge, such as those generated during electrostatic discharge (ESD) events. For example, integrated circuits (ICs) may be exposed to electrostatic charges during manufacturing of the integrated circuit (wafer level), handling of the integrated circuit after packaging and/or handling of a printed circuit board after assembly. In some cases, an integrated circuit may be exposed to the charges that arise from the use of plasma etching techniques or other fabrication processes that produce charged particles. In other cases, a packaged integrated circuit may be exposed to electrostatic charges when a person inadvertently touches the exposed pins on the circuit package, or when the package becomes electrostatically charged due to movement of the package across an electrically-conductive surface.
The electrostatic charges transferred during an ESD event can inflict significant damage to sensitive components of an integrated circuit. For example, transistors and other electrical devices on an integrated circuit may be damaged when an excessive amount of charge is transferred between one or more pins of the integrated circuit and another conducting object in a short time period, usually between tens and hundreds of nanoseconds. The transferred charge (referred to as electrostatic discharge) may develop voltages, which may be large enough to break down insulating films on the circuit (such as gate oxides), or dissipate sufficient energy to cause electro-thermal failures in the circuit (such as contact spiking, silicon melting and metal interconnect melting).
For this reason, many attempts have been made to protect integrated circuits, with particular attention to the problem of protecting field effect transistor (FET) devices and other sensitive circuitry from ESD events. In some cases, ESD protection devices may be connected between the input/output (I/O) pads and internal circuitry of an IC to redirect the energy generated during an ESD event away from the sensitive circuitry. Protection devices may also be connected to power supply pads or between power supply buses to prevent damage during ESD events.
In some cases, ESD protection devices may use “snapback devices,” or devices which rely on parasitic bipolar devices, including bipolar junction transistors (BJTs) and thyristors which are inherent in most semiconductor integrated circuits. These bipolar devices can include those devices normally considered parasitic devices in technologies that use field effect transistors (FET) such as complementary metal-oxide-semiconductor (CMOS) based integrated circuits. During an ESD event, the bipolar device can enter a conductive state to safely dissipate the ESD discharge.
For example, a grounded or floating gate n-channel FET (NFET) may be used as an ESD protection device (100) by connecting the drain terminal of the NFET (110) to an external pin (120) of the integrated circuit, and the source terminal of the NFET to ground, as shown in FIG. 1A. The gate terminal of the NFET may either be floating or be connected to ground. During normal operation of the integrated circuit, the NFET is not active (i.e., has a gate-to-source voltage equal to zero volts, as shown in FIG. 1A), and thus, provides a high-impedance path from the external pin to ground. The ESD protection NFET has thus no significant effect during normal operation of the integrated circuit.
However, during ESD events, the ESD protection device relies on a “snapback” mechanism that provides a low impedance path between the drain and source terminals of the NFET, and redirects potentially damaging ESD charge away from the sensitive circuit elements. In the snapback region (FIG. 1C), the parasitic lateral npn bipolar junction transistor (130) (FIG. 1A) associated with the NFET provides a low-impedance path between the “zapped” pin (120) (FIG. 1A) and ground for the ESD charge injected at the protected integrated circuit pin. The “zapped” pin refers to the integrated circuit pin for which the ESD event occurs.
Snapback generally occurs when the voltage on the zapped pin increases to a value high enough (e.g., 8 volts for a typical CMOS process) to cause the n drain/p substrate junction of the NFET to break down. FIG. 1B shows a semiconductor cross section of the ESD protection NFET 110, including the parasitic BJT 130 during the breakdown region shown in FIG. 1A. This breakdown, otherwise referred to as avalanche breakdown, causes a hole current near the drain of ESD protection NFET 110 to be injected into the substrate, which in turn, raises the local substrate potential and causes the source-substrate junction to become forward biased. Conduction between the “zapped” pin and ground stops when the ESD charge is removed and the NFET resumes its normal drain-to-source high-impedance state.
Although snapback devices are often used within ESD protection devices, they are not without disadvantages. For example, it is hard to predict/control the behavior of actual snapback devices fabricated in silicon, since the behavior of their parasitic BJTs cannot be accurately simulated (due to the fact that snapback devices operate in a region—the snapback region—which is largely unmodeled) and their parameters can be difficult to control in an actual implementation. The lack of predictability can lead to inferior ESD protection performance, over-designed networks or both. Consequently, such ESD protection schemes can consume relatively large amounts of silicon area and can affect the stand-by current budgets of the chips they are used in.
Active shunt networks (otherwise referred to as “actively switched networks”, or “rail-based networks”) represent another method used to implement ESD protection. Within these networks, a control circuit is used to activate the turn on of certain devices (e.g., ESD clamps), which conduct the ESD current through an actively switched network. The control circuit is capable of differentiating between normal operation of the integrated circuit and an ESD event. The control circuit which detects the ESD event is commonly called an “ESD trigger circuit”. In contrast to the snapback ESD protection method described above, active shunt ESD protection networks can be simulated using conventional circuit simulators, resulting in more predictable protection from ESD discharges, which can take comparatively less area for the same ESD performance.
In some cases, an active shunt ESD circuit 200 may include a plurality of diodes, an ESD trigger circuit 210 and an active shunt device 220, as shown in FIG. 2. For example, diodes D1, D2 may be coupled to an external pin of an integrated circuit (e.g., a “zapped pin”) to redirect ESD current away from the protected internal circuitry (230) during an ESD event. The trigger circuit (210) may be coupled for detecting an ESD event at the zapped pin and for activating the active shunt device (e.g., a single NFET) in response thereto. In some cases, the active shunt device 220 may be referred to as an “ESD clamp” or a “current switch”. Once activated, the ESD clamp and diodes may redirect current away from the sensitive circuitry by transferring the current from the zapped pin to a ground supply pin. In most cases, the ESD clamp may be activated only if the slew rate of the zapped pin (i.e., the rate at which the voltage supplied to the zapped pin changes over time) is determined to correspond to an ESD event. In other words, the ESD clamp is designed to not become active during normal operational modes of the integrated circuit or during power-up of the integrated circuit.
The active shunt ESD protection method described above provides several advantages over conventional ESD protection methods that use snapback devices. First of all, ESD protection network circuit behavior can be accurately simulated and controlled by using devices (such as ESD clamps), which operate in the linear or saturation regions of the current-to-voltage (IV) curve, as shown in FIG. 1C. In addition, active shunt ESD circuits often require fewer devices to provide the same amount of ESD protection, and thus, consume less power and area than snapback ESD circuits. Active shunt ESD circuits may also provide better protection at much higher ESD voltages (e.g., up to about 4000 volts) than those using snapback devices (e.g., up to about 1500 volts).
However, active shunt ESD circuits may not provide adequate ESD protection in all cases. In particular, the behavior of the trigger circuit is often hard to control over process variations. For example, the ESD trigger circuit operates by comparing a voltage signal, which is proportional to the voltage slew rate at the zapped pin, with a threshold voltage of a FET transistor included within the trigger circuit. In addition to the slew rate, the voltage signal is determined by several components included within the trigger circuit. Process variations within any one of these components may influence the operation of the trigger circuit by shifting the respective voltage signal to a substantially higher or lower level. In some cases, the trigger circuit may fail to detect a true ESD event when process variations cause the voltage signal to be shifted to a level below the threshold voltage (i.e., trip point) of the trigger circuit. Such failure may allow a potentially damaging electrostatic charge to be supplied to the internal circuitry of an integrated circuit.
One solution to the problem is to adjust the sensitivity of the ESD trigger circuit based on experimental data. For example, the ESD event sensitivity of a particular trigger circuit design may be tested after the respective integrated circuit has been fabricated. If the active shunt ESD protection network fails to trigger during an ESD event, the sensitivity of the trigger circuit may be increased in order to generate the desired voltage level. Once the appropriate changes are made, the integrated circuit may be taped-out again and the ESD protection may be re-verified in the lab once the circuit is fabricated. The process may then continue by trial-and-error until the trigger circuit is provided with sufficient sensitivity to detect ESD events (i.e., the ESD protection provided to the integrated circuit meets certain ESD requirements).
Unfortunately, such a process is time consuming and costly. In addition, the ESD circuits resulting from such a process cannot be reused for other chips (e.g., with different sizes and/or ESD requirements). Therefore, a need remains for an improved ESD protection device that overcomes the disadvantages set forth above. More specifically, a need remains for an improved ESD trigger circuit design that allows ESD event sensitivity to be reconfigured without incurring the additional cost and time associated with the trial-and-error process described above.